Since its introduction in the late 1960's, scan-based testing has gained a wide acceptance as a structured design-for-test (DFT) methodology. This methodology connects memory elements such as flip-flops and latches in a circuit to form scan chains and uses them to make internal nodes of the circuit highly controllable and observable. The controllability and observability enables high-quality automated test generation for large industrial circuit designs.
A commonly used scheme of the scan-based testing is test-per-scan. In a test-per-scan system, a test pattern is first shifted into scan chains and subsequently applied to the circuit-under-test. The test responses generated by the circuit-under-test are then captured by and shifted out of the scan chains for analysis. In this testing scheme, the shifting in and out operations require much more clock cycles to perform than the actual testing (i.e. launching and capturing) operation does. Moreover, in part due to power concerns, the shifting clock is usually kept slower than the clock for the circuit's normal operation. This further increases time for the data loading and unloading operations.
Consider, for example, a circuit design with 100,000 scan cells. These scan cells are divided into 500 scan chains, each 200 scan cells long. Assume the shifting and the normal operating clock frequencies of 50 MHz and 500 MHz, respectively. Applying 20,000 double-capture test patterns requires 4,000,000 shift cycles at 50 MHz and 40,000 capture cycles at 500 MHz. As a result, as low as 1% of cycles, or just 0.1% of time, is spent on the actual testing operation—applying test data and capturing test response data. If a BIST (built-in self-test) method is used for the same circuit design, the test time efficiency could be even lower. With 100K single-capture test patterns, 20,000,000 cycles are needed for scan shifting while only 100,000 cycles are needed for launching and capturing. Using the same clock frequencies as the above example, 99.95% of test time is spent on scan shifting. The above two examples demonstrate that the test-per-scan scheme, though well developed and widely adopted, is not very efficient with respect to testing time.
An alternative scheme, test-per-clock, has been developed mainly for BIST. In a conventional test-per-clock BIST system, the outputs of a test pattern generator are directly coupled to the inputs of the circuit-under-test. Accordingly, a new test pattern is applied to the circuit-under-test at every test clock cycle.
A 1979 paper by Konemann et al., “Built-in logic block observation techniques,” 1979 IEEE Test Conference, which is incorporated herein by reference, describes such a system referred to as BILBO (built-in logic block observer). A BILBO is composed of a flipflop register with additional gates for shift and feedback operations. Four different operational modes can be performed by the BILBO: a mission mode (normal circuit functional mode with scan cells working as latches), a linear shift register mode, a feedback mode, and a reset mode for register resetting. In the feedback mode, the BILBO can work either as a multiple-input signature register (MISR) for compacting test responses or as a linear feedback shift register (LFSR) for generating pseudorandom test patterns. The latter is accomplished by keeping constant values at the parallel inputs of the scan chain.
The 1979 paper describes an example of a test-per-clock architecture with BILBOs working in pairs. One BILBO in a BILBO pair is configured to operate in the feedback mode functioning as a linear feedback shift register. This LFSR BILBO generates and launches a test pattern every test clock cycle. In the meantime, the other BILBO in the pair is configured to operate also in the feedback mode but functioning as a multiple-input signature generator. This MISR BILBO captures a test response every test clock cycle and compacts it with its previously compacted test response to form a new compacted test response. After a number of test clock cycles, a test response signature is eventually shifted out of the MISR BILBO by switching its operational mode from the feedback mode to the linear shift register mode. The unloaded test response signature can then be analyzed.
Another test-per-clock BIST system is described in a 1989 paper by Krasniewski et al., “Circular self-test path: a low cost BIST technique for VLSI circuits,” IEEE Trans. CAD, vol. 8, pp. 46-55, 1989, which is incorporated herein by reference. This system uses a feedback shift register with the last flipflop being supplied to the first flipflop. This shift register serves simultaneously for test pattern generation and test response compaction.
Compared to the test-per-scan scheme, the test-per-clock scheme is more time-efficient because no slow shifting operation is needed for every test pattern. However, the conventional test-per-clock BIST scheme may have a problem on power consumption. In the traditional test-per-clock BIST scheme, all scan chains change their contents every clock cycle no matter whether they are used for pattern generation or for test response compaction. This can lead to excessive circuit toggling and thus power dissipation. Moreover, the traditional test-per-clock scheme has been developed mainly for BIST. It is desirable to develop a new test-per-clock scheme that not only is more time-efficient than the test-per-scan scheme but also addresses the limitations of the existing test-per-clock scheme. Disclosed below are techniques related to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. More specifically for this disclosure, circuit-topology-based techniques for identifying scan chains for various scan chain configurations are discussed.